1. Field of the Invention
The present invention relates to a method of forming an isolation layer in a semiconductor device manufacturing process. In particular, the present invention relates to an isolation layer forming method for a semiconductor device which can prevent an isolation layer from being etched due to the misalignment of a mask when a contact hole is formed, and thus prevent the surface of a semiconductor substrate from being exposed.
2. Description of the Related Art
With the high integration of a semiconductor device, the spaces between patterns in the semiconductor chip have been gradually narrowed. Accordingly, in a device such as a DRAM of more than 256 megabytes, a modified isolation layer forming process such as a recessed LOCOS (R-LOCOS) process has been used to secure an active region of the device. The R-LOCOS method has been widely used because it has advantages that a bird's beak is hardly generated and thus the active region is secured. However, according to the R-LOCOS method, the isolation layer is apt to be etched due to the limitations of a masking process or misalignment of a mask when a contact hold is formed through a following process. This causes the portion of the semiconductor substrate, from which the isolation layer is removed by etching, to be exposed, thereby resulting in the generation of a junction leakage.
FIGS. 1A to 1H are sectional views illustrating a conventional process of manufacturing a semiconductor device. Referring to FIGS. 1A to 1H, the conventional method of forming an isolation layer in a semiconductor device manufacturing process will be explained in detail.
First, as shown in FIG. 1A, a pad oxide film 12 and a nitride layer 13 are sequentially deposited on a silicon substrate 11, and then a photosensitive pattern 14 is formed on the deposited nitride layer 13.
Thereafter, as shown in FIG. 1B, the nitride layer 13 and the pad oxide film 12 are patterned by an anisotropical etching process using the photosensitive pattern 14 as an etch-blocking layer.
Thereafter, as shown in FIG. 1C, the photosensitive pattern 14 is removed, and then a rinsing process is performed. During the rinsing process, the pad oxide film 12 is partially etched, and an edge portion of the pad oxide film 12 is placed on the lower inside of the nitride layer pattern 13. Next, a nitride film 15 for forming a spacer is deposited on a resultant structure.
Thereafter, as shown in FIG. 1D, the whole upper surface of the nitride film 15 is etched, so that a nitride film spacer 15a is formed on a side wall of the pattern of the nitride layer 13 and the pad oxide film 12.
Thereafter, as shown in FIG, 1E, the portion of the silicon substrate 11 where an isolation layer is to be formed is selectively removed to a depth of about 500 .ANG. by an anisotropic etching process. In FIG. 7E, the reference numeral "A" represents a profile of the portion of the silicon substrate 11 which is joined to the edge portion of the nitride film spacer 15a and which is effected by anisotropically etching the silicon substrate 11.
Thereafter, as shown in FIG. 1F, a field oxide layer 16 is formed on the isolation region by an oxidation process. At this time, the field oxide layer 16 is formed inside the silicon substrate 11 such that it has almost 90 degrees with respect to the surface of the silicon substrate 11.
Thereafter, as shown in FIG. 1G, the pattern of the nitride layer 13 and the nitride film spacer 15a are removed, and then a rinsing process is performed. Next, a transistor, a bit line, etc. (not illustrated), which include an impurity-doped region 17, are formed, an oxide layer is formed as an insulating layer 18, and then a photosensitive pattern 19 for forming a contact hole is formed.
Thereafter, as shown in FIG. 1H, the insulating layer 18 is selectively etched to form the contact hole using the photo- sensitive pattern 19 as an etch-blocking layer. At this time, the edge portion of the field oxide layer 16 is etched as shown as "B" in FIG. 1H due to the limitations of the masking process and the misalignment of the mask, causing the silicon substrate 11 to be exposed. As a result, the junction leakage is generated due to the exposure of the silicon substrate, thereby deteriorating the reliability of the device.